IEEE

Compensation techniques for frequency and gain temperature drift in open-loop VCO-ADCs

Abstract: This manuscript presents two approaches to improve the temperature effects on ring oscillators used in open-loop VCO-ADCs. The first approach is a circuit design optimization, which is based ...
GitHub

clk-vco-pll.c

* vco and pll are very closely bound to each other, "vco needs to program: * mode, m & n" and "pll needs to program p", both share common enable/disable * logic. * clk_register_vco_pll() registers ...
IEEE

A 230-GHz Wideband High-Efficiency Beam-Steering 1 × 2 Phased-Array Signal Source in 40-nm CMOS

Abstract: This work presents a 230-GHz $1\times 2$ phased-array signal source (SS) that integrates a voltage-controlled oscillator (VCO), two 360° phase-shifting amplifier-frequency-multiplier chains ...
GitHub

* drivers/media/i2c/ccs-pll.h

/* op pix clock is for all lanes in total normally */ #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0) #define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1) /* CCS PLL flags */ #define ...
Design-Reuse

PLL (Frequency Synthesizer) IP, Input: 10MHz - 200MHz, Output: 25MHz - 400MHz, UMC 0.11um HS/AE process

Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL, UMC 0.11um HS/AE Logic process, It has lock detector function.