EDN

How to raise the RTL abstraction level and design conciseness with SystemVerilog – Part 2

As discussed in Part 1, this article proposes four steps to raise the abstraction level of current Verilog HDL designs and provide a phase wise approach to migrate to SystemVerilog. In Part 1 we ...
Design-Reuse

Cadence OVM SystemVerilog Solution Enables More Thorough Verification and Reduces Costs at Mitsubishi Electric

SAN JOSE, Calif., 25 Jan 2010-- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that Mitsubishi Electric Corp. has adopted Cadence® ...
Semiconductor Engineering

Working With Custom Checkers In Dynamic Simulation Of Low Power Designs

Power-aware simulators can provide a wide range of automated assertions in the form of dynamic sequence checkers that cover every possible PA dynamic verification scenario. However, design specific PA ...