EDN

Targeting Floating-Point Algorithms for FPGA or ASIC Deployment

Native Floating-Point HDL code generation allows you to generate VHDL or Verilog for floating-point implementation in hardware without the effort of fixed-point conversion. Native Floating-Point HDL ...
EDN

Floating point coprocessor interfaces to virtually any microcontroller

Micromega Corporation releases the uM-FPU V3 Floating Point Coprocessor chip. The uM-FPU V3 chip interfaces to virtually any microcontroller using a SPI interface or I2C interface, making it ideal for ...
insideHPC

Universal Coding of the Reals: Alternatives to IEEE Floating Point

In this video from the Conference on Next Generation Arithmetic (CoNGA) conference in Singapore, Peter Lindstrom from Lawrence Livermore National Laboratory presents: Universal Coding of the Reals: ...
Electronic Design

HPC And “Big Data” Apps Tap Floating-Point Number Compression

Floating-point values contain three fields: a sign bit, exponent bits, and significand or mantissa bits. The IEEE-754 floating-point number format defined a common floating-point format that most ...
Electronic Design

Interview: Markus Levy Highlights The EEMBC Floating Point Benchmark

Wong: EEMBC has been around for more than 16 years, why the recent need for floating-point benchmarks? Levy: While floating-point units in processors have been in use for decades, in recent times ...