EDN

Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success

The physical design implementation of large complex deep sub-micron technologies has evolved to a stage where it is essential to consider every aspect of SoC design and implementation during the ...
Semiconductor Engineering

Enhancing Power Reliability Through Design-Stage Layout Optimization

As integrated circuit (IC) designs continue to scale, the demand for efficient power management, performance optimization and reliable physical layout modification grows more critical. Meeting these ...
Semiconductor Engineering

A New Strategy For Successful Block/Chip Design-Stage Verification

Achieving efficiency in integrated circuit (IC) design while maintaining design quality is not just a goal, but a necessity. Designers constantly strive to strike a balance between ever-tightening ...
Design-Reuse

Using in-design physical verification to reduce tapeout schedules

. Tadahiko Yamamoto is Chief Specialist, Design Methodology Development Group, at Toshiba Corp. . Norikazu Ooishi is Specialist, Design Methodology Group, at Toshiba Corp. Physical designers moving to ...
EDN

Deriving design margins for successful timing closure

With the fast developing technology, the complexity of design is increasing day by day. To meet lower technology challenges and to achieve good silicon yield, SOC design flows have been enhanced and ...